This invention relates to a method of fabricating a field effect transistor, and more particularly to a method of fabricating a field effect transistor by forming an impurity diffusion layer by ion implantation method using a gate electrode as the mask.
Conventionally, in the method of fabricating a field effect transistor, as the process of forming an impurity diffusion layer such as a source and drain region after forming a gate electrode, the method of forming by ion implantation using the gate electrode as the mask is widely employed. At this time, in order to prevent the channeling effect of the impurity ions into the semiconductor substrate, it is a general practice to implant by inclining the normal of the semiconductor substrate surface 11 by .theta. degrees, usually about 7 degrees, with respect to the ion beam incident direction 14 as shown in FIG. 1.
In this method, however, as the device becomes smaller and smaller, the junction depth of the impurity diffusion layer becomes shallower, and the heat treatment is lowered in temperature, which results in a shade or shadow part 26 in the gate electrode 23 as shown in FIG. 2, so that the impurity diffusion layer 25 may be asymmetrical with respect to the gate electrode 23. Moreover, the device having such an assymmetrical shape is also influenced in the electric characteristics. For example, effects of the asymmetrical shape on the electric characteristics in a MOS field effect transistor having an LDD (lightly doped drain) structure are as follows. FIG. 3 is a two-dimensional simulation diagram of impurity distribution in the section along the channel longitudinal direction in an LDD structure MOS transistor fabricated so that the LDD region may be asymmetrical with respect to the gate electrode. In this example, the process and device parameters are as follows. The impurity doping for threshold voltage control is boron with 40 keV, 4.0.times.10.sup.12 dose/cm.sup.2, the impurity doping for the LDD region is phosphorus with 40 keV, 1.0.times.10.sup.13 dose/cm.sup. 2, and the impurity doping for the source and drain region is arsenic with 80 keV, 4.0.times.10.sup.15 dose/cm.sup.2. The gate oxide film thickness is 10 nm, the gate electrode height is 450 nm, the gate electrode length is 0.8 .mu.m, the width of an insulation film sidewall spacer is 0.14 .mu.m, and the total heat treatment process after forming the gate electrode is 30 min at 900.degree. C. The source and drain regions were formed to be symmetrical with respect to the gate electrode. As clear from FIG. 3, the portion becoming the shade or shadow of the gate electrode at the time of ion implantation is the area where the end portion of the LDD region is offset with respect to the end of the gate electrode. The drain current characteristic of the device fabricated with said parameters is given in FIG. 4. The method of fabrication conformed to the method proposed, for example, by Paul J. Tsang et al., "Fabrication of High-Performance LDD FET's with Oxide Sidewall-Spacer Technology," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-29, No. 4, April 1982. In the operation where the source region is offset (forward operation), since a high resistance region is formed at the source side, the drain current (ID) becomes lower. On the other hand, in the operation where the drain region is offset (reverse operation), a high resistance region is formed at the drain side, and the saturation voltage is higher, so that the drain current becomes higher. Thus, when the impurity diffusion layer becomes asymmetrical to the gate electrode, an asymmetricity occurs in the electric characteristics of the device, and it is hard to apply into a highly integrated circuit.